1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device comprised of MOS transistors having a floating gate, and a method for manufacturing the same.
2. Description of the Prior Art
A MOS transistor having a floating gate is disclosed in U.S. Pat. Nos. 3,868,187 and 3,984,822. FIGS. 1 to 3 show a nonvolatile semiconductor memory cell 20 having an ordinary floating gate. FIG. 1 shows a plan view of the nonvolatile semiconductor memory cell, FIG. 2 is a cross-sectional view as taken along line II--II in FIG. 1 and FIG. 3 is a cross-sectional view as taken along line III--III in FIG. 1. The memory cell 20 of this type is known in the art. FIGS. 2 and 3 show the state in which capacitances are simultaneously formed in the memory cell 20. The memory cell 20 has a capacitance C1 between a floating gate 22 and a control gate 24, a capacitance C2 between the floating gate 22 and a channel region 26, a capacitance C3 between the floating gate 22 and a P-type semiconductor substrate 28 except for the channel region 26, a capacitance C4 between the floating gate 22 and an N.sup.+ -type drain region 30 and a capacitance C5 between the floating gate 22 and an N.sup.+ -type source region 32. The floating gate 22 and control gate 24 are formed of a polycrystalline silicon. The floating gate 22, control gate 24 and semiconductor substrate 28 are insulated from each other by an insulating layer 34 made of SiO.sub.2.
Control gates 24 of memory cells 20 are connected to the corresponding row lines of a semiconductor memory and drain regions 30 of the memory cells 20 are connected to column lines of the semiconductor memory to provide a memory matrix. When data is written into the memory cell 20, a high voltage of, for example, 25 V is applied to selected row and column lines of the semiconductor memory.
Since the drain regions of the other memory cells 20 are connected to the selected column lines and the control gates 24 of the other memory cells 20 are connected to nonselected row lines (zero voltage is applied to the control gate 24), no data is written to the other memory cells 20. With the drain voltage of the other memory cells 20 (i.e. the memory cells each having the control gate 24 to which zero volt is applied and the drain 30 to which high voltage is applied) indicated by V.sub.D, the potential V.sub.F of the floating gate 22 of the memory cell 20 will be given below ##EQU1## bearing the above-mentioned capacitances C1 to C5 in mind.
For simplicity, the capacitance C4 between the drain region 30 and the floating gate 22 is determined by a distance (lateral diffusion distance) X.sub.j over which the drain region 30 extends toward the substrate portion below the floating gate 22 (see FIG. 2). As generally used in the art, the width FW of the floating gate is assumed to be three times the channel width. The length of the floating gate is represented by FL.
Now assume that at FL=5 .mu.m and X.sub.j =1.2 .mu.m the thickness of the gate oxide is 1,000 .ANG. (0.1 .mu.m), that a distance between the floating gate 22 and the control gate 24 is 1,500 .ANG. (0.15 .mu.m) and that a distance between the floating gate 22 and the semiconductor substrate 28 except for the channel region 26 is 7,000 .ANG. (0.7 .mu.m). The capacitance C of the capacitor of an area S as prepared by filling a material of a dielectric constant .epsilon. between two conductors spaced a distance d apart from each other is given below, ##EQU2## Thus, ##EQU3## From this, EQU V.sub.F =0.073 V.sub.D ( 2)
If high voltage is applied the control gate and the drain region of one memory cell so as to inject electrons into the floating gate, a potential on the floating gate of the nonselected memory cells (memory cells each of whose control gate voltage is zero) sharing the column line with the one memory cell will be 1.46 V from Equation (2) when the each drain voltage V.sub.D of the nonselected memory cells is 20 V. That is, the nonselected memory cells are in the same state as when 1.46 V is applied to the floating gate. Thus, in the writing operation, the floating gate voltage of the nonselected memory cell indicates 1.46 V by only applying 20 V to the drain of the memory cell. Accordingly, the threshold voltage V.sub.TH of the memory cell as measured from the floating gate voltage should be set at 1.46 V or above. If, however, the threshold voltage is raised the current flowing through the memory cell is reduced when data is read out therefrom. Consequently, it consumes a long time to charge or discharge the column line, causing data to be read out of the memory cell at a low speed. Hitherto, therefore, the threshold voltage has been lowered to such extent as allows negligible leakage current to flow through the nonselected memory cell in the writing operation. In the ordinary memory cell, the above-mentioned threshold voltage V.sub.TH is set at about 1 V so as to read out the stored data of memory cells rapidly. That is, when the floating gate voltage is greater than 1 V, the memory cell transistor is rendered conductive. When in this case 20 V is applied to the selected column line in the writing operation, electric current, though smaller, flows through the nonselected memory cell connected to the selected column line. If a greater memory capacity is involved i.e. more memory cell is formed on the same semiconductor chip, more memory cell is connected to the same column line and the sum of electric currents through the nonselected memory cells becomes a level which can not be disregarded. As a result, a problem tends to arise that due to such leakage current a potential on the column line becomes lower at writing operation and thus a longer writing time will be required. Moreover, since at the writing time electric current flows through the nonselected memory cell, an erroneous writing operation tends to occur with respect to the nonselected memory cell.
In order to cope with the lowering of the potential on the column line, a method is proposed which provides a greater current carrying capability to a load transistor for use in a data writing operation. Suppose that a writing operation is effected with respect to the nonselected transistor connected to the same column line (electrons are injected into the floating gate) and thus the threshold voltage V.sub.TH becomes greater. In this case, excess current flows from the load transistor to the selected transistor, there being a risk that the memory cell will suffer breakdown.
According to Equation (1) it is necessary that in order to make a potential on the floating gate small in the state of a predetermined drain potential V.sub.D the capacitance C4 between the floating gate and the drain region be decreased. In order to decrease the capacitance C4 without changing the size, for example the channel length, of the memory cell, all that is necessary is to decrease the lateral diffusion distance X.sub.j of the drain region.
The drain region of the conventional memory cell 20 is self-aligned with the floating gate 22 as a mask as shown in FIG. 4. In this case, the gate electrode 38 of a MOS transistor 36 of a peripheral circuit is formed simultaneously with the formation of the above-mentioned floating gate 22. The drain region 40 and source region 42 of the MOS transistor 36 are self-aligned with the gate 38 as a mask. In consequence, the drain and source regions of the memory cell 20 and the MOS transistor 36 of a peripheral circuit, each, has the same lateral diffusion distance X.sub.j. If in this case the diffusion distance X.sub.j is decreased to make the capacitance C4 smaller, the junction depth of the memory cell 20 and the MOS transistor 36 of peripheral circuit becomes smaller, causing the breakdown voltage of the PN junction to be lowered. In order to decrease the diffusion distance X.sub.j with the breakdown voltage maintained at a high level, it is only necessary to decrease the impurity doping concentration of the N.sup.+ region of FIG. 4. However, the resistive value of the N.sup.+ region becomes higher and a power loss is increased, resulting in the slowing down of the operation speed of the circuit.